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Blog / 20 Dec 2025

Microprocessor DHRUV64: Strengthening Self-Reliance in Semiconductor Technology

Context:

On 15 December 2025, the Ministry of Electronics and Information Technology (MeitY) announced the launch of DHRUV64, India’s first entirely indigenous 1.0 GHz, 64-bit dual-core microprocessor. It has been developed under the Microprocessor Development Programme (MDP) by the Centre for Development of Advanced Computing (C-DAC).

Key Features of DHRUV64:

      • Architecture: DHRUV64 is a 64-bit, dual-core processor operating at 1.0 GHz, designed with modern architectural features such as superscalar design and out-of-order execution, enabling improved multitasking and higher performance.
      • Open-Source RISC-V ISA: The processor is based on the RISC-V open instruction set architecture, which is royalty-free and reduces dependence on proprietary foreign technologies.
      • Design and Fabrication Ecosystem: DHRUV64 is part of India’s Digital India RISC-V (DIR-V) Programme. It has been designed by C-DAC and supported by national initiatives promoting indigenous chip design, verification, and prototyping.

India takes a big tech step by launching DHRUV64, its first indigenous 1.0  GHz 64-bit microprocessor, strengthening self-reliance in defence, telecom,  and critical semiconductor technology. #DHRUV64 #MakeInIndia #TechNews

Applications and Use Cases:

DHRUV64 is intended for deployment across a wide range of sectors:

      • Telecommunications: 5G infrastructure and networking equipment requiring reliable and secure processing capabilities.
      • Industrial Automation: Manufacturing systems, robotics, and control units that demand efficient processors for real-time operations.
      • Automotive Systems: Embedded computing applications in vehicles, including safety systems, infotainment, and vehicle control units.
      • Consumer Electronics and IoT: Smart devices, sensors, and connected appliances that benefit from an indigenous and trusted compute platform.
      • Strategic and Defence Applications: Potential use in defence systems where supply-chain security, reliability, and hardware trustworthiness are critical.

Strategic and National Importance:

      • Reducing Import Dependence: DHRUV64 lowers India’s reliance on imported microprocessors, thereby enhancing national security and digital sovereignty.
      • Strengthening the Domestic Ecosystem: It builds upon earlier indigenous processor initiatives such as SHAKTI, AJIT, VIKRAM, and THEJAS64, reinforcing India’s capabilities in chip design and prototyping.
      • Supporting Innovation: The royalty-free RISC-V architecture enables startups, academia, and industry to develop and scale indigenous hardware and software solutions.
      • Skill Development and R&D: The project converts India’s theoretical and design expertise into deployable products, strengthening research pipelines and paving the way for next-generation processors such as Dhanush.

Policy and Programmatic Support:

The development of DHRUV64 is backed by a coordinated government-led policy framework:

      • The Digital India RISC-V (DIR-V) Programme promotes open-architecture chip design and prototyping.
      • The Microprocessor Development Programme (MDP) provides funding and strategic direction for indigenous processor development.
      • Complementary initiatives such as Chips to Startup (C2S), the Design-Linked Incentive (DLI) Scheme, and the India Semiconductor Mission (ISM) support the broader semiconductor design and manufacturing ecosystem.

Together, these initiatives align with the national vision of Aatmanirbhar Bharat (self-reliant India) in advanced technologies and critical digital infrastructure.

Conclusion:

The launch of DHRUV64 represents a significant milestone in India’s journey towards technological self-reliance in semiconductors. By reducing import dependence and strengthening the indigenous chip ecosystem, DHRUV64 provides a trusted, homegrown computing platform for diverse applications and positions India as an emerging player in global semiconductor design and innovation.